Effect of gate dielectric on threshold voltage of Nanoscale MOSFETS

An integrated circuit (IC) dimensions continue to decrease, RC delay, crosstalk noise, and power dissipation of the interconnect structure become limiting factors for ultra-large-scale integration of integrated circuits. Modern microcircuits may have eight metal layers, each separated by only 0.1 micrometers. RC delays and cross talk rather than transistor speed are now the major performance limitations. The semiconductor industry has responded by developing copper metallization to replace aluminum and lower dielectric constant materials to replace silicon oxide. Materials with different low dielectric constant are being analyzed to replace silicon dioxide as inter level dielectrics. In this paper, how the dielectric constant is affecting the threshold voltage is first discussed. The simulation works are carried using MATLAB, SCHRED software. Based on the results obtained on the effect of kvalues on VT in nano MOSFETs, the low-k material (PTFE) is suggested as a suitable material for the development of MOSFET as well as interconnects.